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drv8860 , drv8860a slrs065d ? september 2013 ? revised october 2015 drv8860x 38-v 8-channel serial interface low-side driver 1 features 3 description the drv8860 provides an 8-channel low side driver 1 ? 8-channel protected low-side driver with overcurrent protection and open/shorted load ? eight nmos fets with overcurrent protection detection. it has built-in diodes to clamp turn-off ? integrated inductive catch diodes transients generated by inductive loads, and can be used to drive unipolar stepper motors, dc motors, ? serial interface relays, solenoids, or other loads. ? open/short load detection (drv8860 only) the pwp package can supply up to 330 ma 8 ? configurable 100% output timing channel and the pw package can supply up to 200 ? configurable pwm duty cycle ma 8 channel continuous output current. a single ? continuous current driving capability channel can deliver up to 560 ma continuous output current. ? 560 ma (single channel on) pw and pwp ? 200 ma (8 channels on) pw a serial interface is provided to control the drv8860 output drivers, configure internal setting register and ? 330 ma (8 channels on) pwp read the fault status of each channel. drv8860 ? support parallel configuration devices can be daisy-chained together to use a single ? 8 v to 38 v supply voltage range serial interface. energizing-time and holding-pwm- duty cycles are configurable through serial interface ? input digital noise filter for noise immunity as well. these functions allow for cooler running than ? internal data read back capability for reliable always-on solutions. control internal shutdown functions are provided for ? protection and diagnostic features overcurrent protection, short-circuit protection, ? overcurrent protection (ocp) undervoltage lockout, and overtemperature. ? open load detection (ol) drv8860a does not include open load detection. fault information for each channel can be read out ? overtemperature shutdown (ots) through serial interface and indicated by an external ? undervoltage lockout (uvlo) fault pin. ? individual channel status report device information (1) ? fault condition alarm part number package body size (nom) 2 applications tssop (16) 5.00 mm 6.40 mm drv8860 htssop (16) 5.00 mm 4.40 mm ? relays, unipolar stepper motors drv8860a tssop (16) 5.00 mm 6.40 mm ? solenoids, electromagnetic drivers (1) for all available packages, see the orderable addendum at ? general low-side switch applications the end of the datasheet. ? led driver with dimmer functionality (drv8860a) 4 simplified schematic 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. vm 8 to 38 v nfault enable latch din clk dout drv8860 8 channel serial interface low-side driver 100 200 300 400 500 600 12.5 0 0 duty cycle (%) peak current (ma/output) n = 1 n = 2 n = 4 n = 8 n: number of outputs active 25.0 37.5 50.0 62.5 75.0 87.5 100.0 productfolder sample &buy technical documents tools & software support &community
drv8860 , drv8860a slrs065d ? september 2013 ? revised october 2015 www.ti.com table of contents 8.4 device functional modes ........................................ 13 1 features .................................................................. 1 8.5 programming ........................................................... 15 2 applications ........................................................... 1 8.6 register maps ......................................................... 26 3 description ............................................................. 1 9 application and implementation ........................ 27 4 simplified schematic ............................................. 1 9.1 application information ............................................ 27 5 revision history ..................................................... 2 9.2 typical application ................................................. 27 6 pin configuration and functions ......................... 4 10 power supply recommendations ..................... 29 7 specifications ......................................................... 5 10.1 power supply and logic sequencing ................... 29 7.1 absolute maximum ratings ...................................... 5 11 layout ................................................................... 30 7.2 handling ratings ...................................................... 5 11.1 layout guidelines ................................................. 30 7.3 recommended operating conditions ....................... 5 11.2 layout example .................................................... 30 7.4 thermal information ................................................. 5 11.3 thermal consideration .......................................... 31 7.5 electrical characteristics ........................................... 6 12 device and documentation support ................. 32 7.6 timing requirements ................................................ 6 12.1 community resources .......................................... 32 7.7 typical characteristics .............................................. 7 12.2 trademarks ........................................................... 32 8 detailed description .............................................. 7 12.3 electrostatic discharge caution ............................ 32 8.1 overview ................................................................... 7 12.4 glossary ................................................................ 32 8.2 functional block diagram ......................................... 8 13 mechanical, packaging, and orderable 8.3 feature description ................................................... 9 information ........................................................... 32 5 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision c (october 2014) to revision d page ? added i (vm) max = 4.5 v ......................................................................................................................................................... 6 ? added i off for drv8860a ..................................................................................................................................................... 6 ? changed t ocp from: min = 2.7 to: 2.0 s ............................................................................................................................. 6 ? updated functional block diagram ........................................................................................................................................ 8 changes from revision b (july 2014) to revision c page ? added drv8860a part to datasheet. .................................................................................................................................... 1 ? added caption to figure 7 ................................................................................................................................................... 13 ? added caption to figure 8 ................................................................................................................................................... 13 ? moved the serial control interface information into the programming section of the datasheet ........................................ 15 ? moved the register maps information into the detailed description section of the datasheet ........................................... 26 ? changed figure 35 from a black background to a white background ................................................................................. 28 ? added caption to figure 37 ................................................................................................................................................. 30 ? changed title from: thermal information to: thermal consideration ................................................................................ 31 changes from revision a (november 2013) to revision b page ? added feature: serial interface .............................................................................................................................................. 1 ? changed the features list for: continuous current driving capability ................................................................................... 1 ? deleted features: programmable current profile .................................................................................................................. 1 ? updated the application list .................................................................................................................................................. 1 ? changed description sentence from: these functions allow for lower temperature operation rather than traditional always-on solutions. to: these functions allow for cooler running than traditional always-on solutions ............................... 1 ? added the handling ratings table .......................................................................................................................................... 5 2 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: drv8860 drv8860a
drv8860 , drv8860a www.ti.com slrs065d ? september 2013 ? revised october 2015 ? changed the min value for vm in the recommended operating conditions table from: 8.2 v to: 8 v .............................. 5 ? added httssop (pwp) to the thermal information table ................................................................................................... 5 ? changed v il from: min = - to: 0 v, typ = 0.6 v to: - ........................................................................................................ 6 ? changed v ih from: min = 2 v to: 1.5 v, max = - to: 5.3 v ............................................................................................... 6 ? changed v hys from: min = - to: 100 mv, typ = 0.45 v to: - ............................................................................................ 6 ? added the timing requirements table ................................................................................................................................... 6 ? added the overview section .................................................................................................................................................. 7 ? changed the description of the recommended output current section ................................................................................ 9 ? deleted the example output configuration section. ............................................................................................................ 11 ? changed the serial control interface description text ......................................................................................................... 15 changes from original (september 2013) to revision a page ? added features: programmable current profile .................................................................................................................... 1 ? changed the min value for vm in the recommended operating conditions table from: 8 v to: 8.2 v .............................. 5 ? added the example output configuration section. .............................................................................................................. 11 copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 3 product folder links: drv8860 drv8860a
drv8860 , drv8860a slrs065d ? september 2013 ? revised october 2015 www.ti.com 6 pin configuration and functions pwp (htssop) package (top view) pw (tssop) package (top view) pin functions i/o name pin description external components or connections (1) gnd 5 ? device ground all pins must be connected to ground connect to motor supply voltage. bypass to gnd with a 0.1 f ceramic capacitor vm 1 ? motor power supply plus a 10 f electrolytic capacitor. output stage enable logic high to enable outputs, logic low to disable outputs. internal logic and enable 8 i control input registers can be read and written to when enable is logic low. internal pulldown. latch 4 i serial latch signal refer to serial communication waveforms. internal pulldown. rising edge clocks data into part for write operations. falling edge clocks data out clk 3 i serial clock input of part for read operations. internal pulldown. din 2 i serial data input serial data input from controller. internal pulldown. dout 6 o serial data output serial data output to controller. open-drain output with internal pullup. logic low when in fault condition. open-drain output requires external pullup. nfault 7 od fault faults: ocp, ots, uvlo, ol (drv8860 only) out1 16 o low-side output 1 nfet output driver. connect external load between this pin and vm out2 15 o low-side output 2 nfet output driver. connect external load between this pin and vm out3 14 o low-side output 3 nfet output driver. connect external load between this pin and vm out4 13 o low-side output 4 nfet output driver. connect external load between this pin and vm out5 12 o low-side output 5 nfet output driver. connect external load between this pin and vm out6 11 o low-side output 6 nfet output driver. connect external load between this pin and vm out7 10 o low-side output 7 nfet output driver. connect external load between this pin and vm out8 9 o low-side output 8 nfet output driver. connect external load between this pin and vm (1) directions: i = input, o = output, od = open-drain output table 1. external components component pin 1 pin 2 recommended 0.1 f ceramic capacitor rated for vm c (vm1) vm gnd 10 f electrolytic capacitor rated for vm r (nfault) v3p3 (1) nfault > 4.7 k (1) v3p3 is not a pin on the drv8860, but a v3p3 supply voltage pullup is required for open-drain output nfault. 4 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: drv8860 drv8860a 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vm din clk latch gnd dout enable nfault out1 out2 out3 out4 out5 out6 out7 out8 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vm din clk latch gnd dout enable nfault out1 out2 out3 out4 out5 out6 out7 out8
drv8860 , drv8860a www.ti.com slrs065d ? september 2013 ? revised october 2015 7 specifications 7.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) min max unit power supply voltage range vm ? 0.3 40 v digital input pin current range enable, latch, clk, din 0 20 ma digital output pin voltage range dout, nfault ? 0.5 7 v digital output pin current dout, nfault ? 0.5 7 v output voltage range outx ? 0.3 40 v output current range outx internally limited a operating virtual junction temperature range, t j ? 40 150 c (1) stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute ? maximum ? rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. (3) power dissipation and thermal limits must be observed 7.2 handling ratings min max unit t stg storage temperature range ? 60 150 c human body model (hbm), per ansi/esda/jedec js-001, all ? 2 2 kv pins (1) v (esd) electrostatic discharge charged device model (cdm), per jedec specification ? 500 500 v jesd22-c101, all pins (2) (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit vm motor power supply voltage range 8 38 v i out low-side driver current capability 560 ma t a operating ambient temperature range ? 40 85 c 7.4 thermal information (1) over operating free-air temperature range (unless otherwise noted) tssop htssop thermal metric unit pw (16 pins) pwp (16 pins) ja junction-to-ambient thermal resistance 103 40.9 c/w r jc(top) junction-to-case (top) thermal resistance 37.9 28.5 c/w r jb junction-to-board thermal resistance 48 23.2 c/w jt junction-to-top characterization parameter 3 0.9 c/w jb junction-to-board characterization parameter 47.4 23.0 c/w r jc(bottom) junction-to-case (bottom) thermal resistance n/a 3.0 c/w (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 5 product folder links: drv8860 drv8860a
drv8860 , drv8860a slrs065d ? september 2013 ? revised october 2015 www.ti.com 7.5 electrical characteristics t a = 25 c, over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max unit power supplies i (vm) vm operating supply current vm = 24 v 3 4.5 ma v (uvlo) vm undervoltage lockout voltage vm rising 8.2 v logic-level inputs (din, clk, latch, enable) v il input low voltage 0 0.7 v v ih input high voltage 1.5 5.3 v v hys input hysteresis 100 mv i il input low current v in = 0 ? 20 20 a i ih input high current v in = 3.3 v 100 a r pd input pulldown resistance 100 k nfault, dout outputs (open-drain outputs) v ol output low voltage i o = 5 ma 0.5 v i oh output high leakage current v o = 3.3 v, nfault ? 1 1 a r pu input pullup resistance dout only (pull up to internal 5.7 v) 1.4 k low-side fet drivers vm = 24 v, i o = 150 ma, t j = 25 c 1.5 r ds(on) fet on resistance vm = 24 v, i o = 150 ma, t j = 85 c 1.8 vm = 24 v, t j = 25 c, drv8860 0 30 i off off-state leakage current a vm = 24 v, t j = 25 c, drv8860a -0.5 0.5 high-side free-wheeling diodes v f diode forward voltage vm = 2 4v, i o = 150 ma, t j = 25 c 0.9 v protection circuits i ocp overcurrent protection trip level each channel separately monitored 620 ma i ol open load detect pull-down current per channel, drv8860 only 30 a v ol open load detect threshold voltage per channel, drv8860 only 1.2 v t tsd thermal shutdown temperature die temperature 150 160 180 c t hys thermal shutdown hysteresis die temperature 35 c pwm chopping frequency duty cycle is > 25% 45 50 55 f pwm pwm chopping frequency duty cycle is 25% 22 25 28 khz duty cycle is 12.5% 11 12.5 14 7.6 timing requirements min typ max unit t f fall time i o = 150 ma, vm = 24 v, resistive load 50 300 ns overcurrent protection deglitch t ocp vm = 24 v 2.0 3.0 3.85 s time t ol open load detect deglitch time each channel separately monitored 14 17 20 s 6 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: drv8860 drv8860a
drv8860 , drv8860a www.ti.com slrs065d ? september 2013 ? revised october 2015 7.7 typical characteristics figure 1. output on resistance figure 2. vm operating supply current 8 detailed description 8.1 overview the drv8860 is an integrated 8-channel low side driver with overcurrent protection and open/short detection. it has built-in diodes to clamp turn-off transients generated by inductive loads, and can be used to drive unipolar stepper motors, dc motors, relays, solenoids, or other loads. drv8860 can supply up to 200 ma x 8 channel continuous output current. the current driving capability increases with lower pwm duty cycle. a single channel can deliver up to 560 ma continuous output current. refer to the current capability table for details. a serial interface is provided to control the drv8860 output drivers, configure internal register settings, and read the fault status of each channel. multiple drv8860 devices can be daisy-chained together to use a single serial interface. energizing-time and holding-pwm-duty cycle are configurable through the serial interface as well. these functions allow for cooler running than traditional always-on solutions. internal shutdown functions are provided for overcurrent protection, short-circuit protection, under voltage lockout and over temperature. drv8860 can diagnosis an open load condition. drv8860a does not include open load detection. fault information for each channel can be read out through serial interface and is indicated by an external fault pin. copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 7 product folder links: drv8860 drv8860a 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 0 10 20 30 40 50 r ds(on) ( : ) vm voltage (v) c004 3.20 3.25 3.30 3.35 3.40 0 10 20 30 40 50 i (vm) current (ma) vm voltage (v) c004
drv8860 , drv8860a slrs065d ? september 2013 ? revised october 2015 www.ti.com 8.2 functional block diagram 8 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: drv8860 drv8860a drv8860 only ol vm out1 gate drive, ocp, open load vm vm out1 gate drive, ocp, open load vm out1 gate drive, ocp, open load vm out1 gate drive, ocp, open load vm out1 gate drive, ocp, open load vm out1 gate drive, ocp, open load vm out1 gate drive, ocp, open load vm out1 gate drive, ocp, open load vm 10 f power logic ldo gate drive vm dout latch clk din serial interface core logic enable output nfault protection overcurrent undervoltage thermal open load gnd ppad (pwp package only) 0.1 f
drv8860 , drv8860a www.ti.com slrs065d ? september 2013 ? revised october 2015 8.3 feature description 8.3.1 recommended output current drv8860 current capability will depend on several system application parameters such as system ambient temperature, maximum case temperature, and overall output duty cycle. the pwp package provides a better heatsinking capability through the powerpad ? ; and therefore, is cable of driving higher output current or operating at a slightly lower temperature than the device in pw package. output current recommendation (pw package) t a = 25 c configuration output current capacity 1x output on (100% duty cycle) 566 ma 2x outputs on (100% duty cycle) 400 ma per output 4x outputs on (100% duty cycle) 283 ma per output 8x outputs on (100% duty cycle) 200 ma per output figure 3. output current capacity vs duty cycle for pw package copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 9 product folder links: drv8860 drv8860a 100 200 300 400 500 600 12.5 0 0 duty cycle (%) peak current (ma/output) n = 1 n = 2 n = 4 n = 8 n: number of outputs active 25.0 37.5 50.0 62.5 75.0 87.5 100.0
drv8860 , drv8860a slrs065d ? september 2013 ? revised october 2015 www.ti.com figure 4. maximum current capacity vs duty cycle when paralleling outputs for drv8860pw 10 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: drv8860 drv8860a
drv8860 , drv8860a www.ti.com slrs065d ? september 2013 ? revised october 2015 8.3.2 daisy chain connection two or more drv8860 devices may be connected together to use a single serial interface. the sdatout pin of the first device in the chain is connected to the sdatin pin of the next device. the sclk, latch, reset, and nfault pins are connected together. timing diagrams are shown in figure 5 and figure 6 for the configuration of single devices, as well as two devices in daisy-chain connection. figure 5. single device connection figure 6. daisy-chain connection copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 11 product folder links: drv8860 drv8860a host processor drv8860 device #1 latch din 1 clk dout 1 out1 8 ~38 v gpio gpio gpio gpio out8 drv8860 device #2 latch din 2 clk dout 2 out1 out8 host processor drv8860 latch din clk dout nfault out1 8 ~38 v gpio gpio gpio gpio gpio out8
drv8860 , drv8860a slrs065d ? september 2013 ? revised october 2015 www.ti.com 8.3.3 protection circuits the drv8860 is fully protected against undervoltage, overcurrent and overtemperature events. 8.3.3.1 overcurrent protection (ocp) when output current exceeds ocp trigger level, corresponding channel will be automatically turned off. nfault pin will be set low and corresponding ocp flag in fault register will be set to 1. over current faults are automatically cleared whenever the corresponding output is turned off by setting the data register bit to ? 0 ? . alternatively, a fault reset special command will also clear this value. in either case, once all bits in the fault register are clear, nfault is released. 8.3.3.2 open load detection (ol) - drv8860 only when any output is in off status (the corresponding data register bit is set to ? 0 ? ), a current sink pulls the node down with approximately 30 a. if the voltage on the pin is sensed to be less than 1.2 v, then an open load condition is reported. nfault is driven low and the ol bit of the fault register (f8:f1) corresponding to the specific channel is set. open load faults are automatically cleared whenever the corresponding output is turned on by setting the data register bit to ? 1 ? . alternatively, a fault reset special command will also clear this value. in either case, once all bits in the fault register are clear, nfault is released. 8.3.3.3 thermal shutdown (tsd) if the die temperature exceeds safe limits, all outputs will be disabled, and the nfault pin will be driven low. once the die temperature has fallen to a safe level, operation will automatically resume. the nfault pin will be released after operation has resumed. 8.3.3.4 undervoltage lockout (uvlo) if at any time the voltage on the vm pin falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled and internal logic will be reset. operation will resume when vm rises above the uvlo threshold. nfault will not be asserted in this condition. 8.3.3.5 digital noise filter the drv8860 features an internal noise filter on all digital inputs. in a noisy system, noise may disturb the serial daisy-chain interface. without an input filter, this noise may result in an unexpected behavior or output state. the digital input filter is capable of removing unwanted noise frequencies while allowing fast communication over the serial interface. 12 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: drv8860 drv8860a
drv8860 , drv8860a www.ti.com slrs065d ? september 2013 ? revised october 2015 8.4 device functional modes 8.4.1 internal registers the drv8860 is controlled with a simple serial interface. there are three register banks that are used during operation: the data register, the control register, and the fault register. register data movement flow and direction will be affected by special command. figure 7. register data movement in default condition, 8 bit shift register data moves into output control register data-reg. copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 13 product folder links: drv8860 drv8860a
drv8860 , drv8860a slrs065d ? september 2013 ? revised october 2015 www.ti.com device functional modes (continued) figure 8. 8 bit shift register data movement 14 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: drv8860 drv8860a
drv8860 , drv8860a www.ti.com slrs065d ? september 2013 ? revised october 2015 8.5 programming 8.5.1 serial control interface drv8860 is using a daisy chain serial interface. data is latched into the register on the rising edge of the latch pin. data is clocked in on the rising edge of clk when writing, and data is clocked out on the falling edge of clk when reading. 8.5.1.1 data writing waveform figure 9. writing data register ? single device figure 10. writing data register ? daisy chan figure 11. writing data register ? data flow copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 15 product folder links: drv8860 drv8860a latch clk din 1 dout 1 / din 2 1 2 3 4 5 6 7 8 xx xx xxx 9 10 11 12 13 14 15 16 xxxxxxxxxxxx data register 1 xxxxxxxxxxxxxxxxxxxxx old data register contents device #1 xxxx xxxx xxxx xxxx a_d8 a_d7 a_d6 a_d5 a_d4 a_d3 a_d2 a_d1 a_d8 a_d7 a_d6 a_d5 a_d4 a_d3 a_d2 a_d1 b_d8 b_d7 b_d6 b_d5 b_d4 b_d3 b_d2 b_d1 data b data register 2 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxx old data register contents device #2 data a latch clk din 1 2 3 4 5 6 7 8 xxxx xxxx xxxx xxxxx xxxxx data register xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx a_d8 a_d7 a_d6 a_d5 a_d4 a_d3 a_d2 a_d1 data a xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx old data register contents
drv8860 , drv8860a slrs065d ? september 2013 ? revised october 2015 www.ti.com programming (continued) 8.5.1.2 fault register reading waveform figure 12. reading fault register ? single device figure 13. reading fault register ? daisy chain figure 14. reading fault register ? data flow 16 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: drv8860 drv8860a latch clk dout 1 / din 2 x x dout 2 control register contents a fault register #1 control register contents b fault register #2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 f16 f15 f14 f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 xxxx xxxx f1 f16 f15 f14 f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 xxxx f1 f16 f15 f14 f13 f12 f11 xxxxxxxxx xxxxxxxxx latch clk 1 2 3 4 5 6 7 8 dout f16 f15 f14 f13 f12 f11 f10 f9 xx xx 9 10 11 12 13 14 15 fault register contents a fault register 16 f8 f7 f6 f5 f4 f3 f2 xxxx f1 xx
drv8860 , drv8860a www.ti.com slrs065d ? september 2013 ? revised october 2015 programming (continued) 8.5.1.3 special command besides output on/off control and fault status reading back, drv8860 has special functions to make system more robust or power efficient. these functions will need special command to initiate the device or configure the internal registers. there are 5 special commands: 1. write control register command 2. read control register command 3. read data register command 4. fault register reset command 5. pwm start command special wave form pattern on clk and latch pin will issue the special command, as below figure 15. special command clk cycles in each part special command part 1 part 2 part 3 part 4 write control register 1 2 2 3 read control register 1 4 2 3 read data register 1 4 4 3 fault register reset 1 2 4 3 pwm start 1 6 6 3 copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 17 product folder links: drv8860 drv8860a latch clk 1 xxx xxx xxx xxx 1 2 1 2 3 3 4 5 6 1 2 3 4 5 6 part 2 part 1 part 3 part 4
drv8860 , drv8860a slrs065d ? september 2013 ? revised october 2015 www.ti.com 8.5.1.3.1 special command: write control register when write-control-register command is issued, the following serial data will be latched into timing and duty control register. figure 16. writing control register ? single device figure 17. writing control register ? daisy chain figure 18. writing control register ? data flow 18 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: drv8860 drv8860a xxxxxxxxxxxxxxxxxxxxxxxxxxxx old control register contents device #1 latch clk din 1 1 2 3 4 5 6 7 8 xxxx xxx xxx a_c8 a_c7 a_c6 a_c5 a_c4 a_c3 a_c2 a_c1 control b 1 xx xx 1 2 1 2 1 2 3 xxxxxxxxx dout 1 / din 2 control register 1 9 10 11 12 13 14 15 16 b_c8 b_c7 b_c6 b_c5 b_c4 b_c3 b_c2 b_c1 a_c8 a_c7 a_c6 a_c5 a_c4 a_c3 a_c2 a_c1 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxx old control register contents device #2 control a control register 2 xxxxxxxxxxxxxxxxxx latch clk din 1 2 3 4 5 6 7 8 control register xxxx xxxx xxxx a_c8 a_c7 a_c6 a_c5 a_c4 a_c3 a_c2 a_c1 control a 1 x x 1 2 1 2 1 2 3 xxxxxxxxx xxxxxxxxxxxxxxxxxx
drv8860 , drv8860a www.ti.com slrs065d ? september 2013 ? revised october 2015 8.5.1.3.2 special command: read control register when read-control-register command is issued, control register content will be copied to internal shift register and following clk will shift this content out from dout pin. this provides a mechanism for system to verify the control register is correctly programmed. figure 19. read control register ? single device figure 20. read control register ? daisy chain figure 21. read control register ? data flow copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 19 product folder links: drv8860 drv8860a latch clk 1 2 3 4 5 6 7 8 dout 1 / din 2 a_c8 a_c7 a_c6 a_c5 a_c4 a_c3 a_c2 a_c1 1 xx xx 1 2 1 2 1 2 3 3 4 dout 2 xxxxxxxxxx 9 10 11 12 13 14 15 xxxxxxxxxxxx control register contents a control register #1 control register contents b control register #2 a_d8 a_d7 a_d6 a_d5 a_d4 a_d3 a_d2 xxxxxxxxxx b_d8 b_d7 b_d6 b_d5 b_d4 b_d3 b_d2 b_d1 16 a_d1 xxx control register contents a latch clk 1 2 3 4 5 6 7 8 dout xxxxx xxxx xxxx a_c8 a_c7 a_c6 a_c5 a_c4 a_c3 a_c2 a_c1 1 x x 1 2 1 2 1 2 3 3 4 control register xxxxxxxxx
drv8860 , drv8860a slrs065d ? september 2013 ? revised october 2015 www.ti.com 8.5.1.3.3 special command: read data register when read-data-register command is issued, internal output data register content will be copied to internal shift register and following clk will shift this content out from dout pin. this provides a mechanism for system to verify the output data is correctly programmed. it makes system more robust in noisy system. figure 22. reading data register ? single device figure 23. reading data register ? daisy chain figure 24. reading data register ? data flow 20 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: drv8860 drv8860a data register contents a latch clk 1 2 3 4 5 6 7 8 a_d8 a_d7 a_d6 a_d5 a_d4 a_d3 a_d2 a_d1 1 x x 1 2 1 2 3 3 4 dout 1 / din 2 data register 1 1 2 3 4 xxxxxxxxxx dout 2 data register contents b data register 2 9 10 11 12 13 14 15 a_d8 a_d7 a_d6 a_d5 a_d4 a_d3 a_d2 xxxxxxxxxx b_d8 b_d7 b_d6 b_d5 b_d4 b_d3 b_d2 b_d1 xxxxxxxxxxxx 16 a_d1 xxx data register contents a latch clk 1 2 3 4 5 6 7 8 xxxxx xxxx a_d8 a_d7 a_d6 a_d5 a_d4 a_d3 a_d2 a_d1 1 xx 1 2 1 2 3 3 4 dout data register 1 2 3 4 xxxxxxxxxxx
drv8860 , drv8860a www.ti.com slrs065d ? september 2013 ? revised october 2015 8.5.1.3.4 special command: fault register reset when fault-register-reset command is issued, internal 16bit fault register will be cleared. system can use this method to clear out all fault condition in every chained device at once. figure 25. fault register reset 8.5.1.3.5 special command: pwm start when fault-register-reset command is issued, output channel will ignore energizing time and directly enter into pwm mode following the setting in control register. figure 26. pwm start command copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 21 product folder links: drv8860 drv8860a latch clk 1 xxx xxx 1 2 1 2 3 outx 3 4 5 6 1 2 3 4 5 6 xxxxxxxxxxxxx xxxxxxxxxxxxx max-on time pwm chopping latch clk 1 xxx xxx xxx 1 2 1 2 3 fault register 1 2 3 4 fault register contents nfault fault condition no fault condition xxxxxxxxxxx xxxxxxxxxxx xxxxxxxxxxx
drv8860 , drv8860a slrs065d ? september 2013 ? revised october 2015 www.ti.com 8.5.1.4 output energizing and pwm control the device output is defined by two stages: energizing phase and pwm phase. during the energizing phase, the channel is turned on with 100% duty cycle for a duration set by control register bits c4:c1. in pwm chopping phase, with the pwm duty cycle defined by control register bits c7:c5. the behavior of each bit in the control register is described in table 2 . table 2. control register settings c8 c7 c6 c5 c4 c3 c2 c1 value description 0 x x x x x x x n/a outputs always in energizing mode 1 x x x 0 0 0 0 0 ms no energizing, starts in pwm chopping 1 x x x 0 0 0 1 3 ms 1 x x x 0 0 1 0 5 ms 1 x x x 0 0 1 1 10 ms 1 x x x 0 1 0 0 15 ms 1 x x x 0 1 0 1 20 ms 1 x x x 0 1 1 0 30 ms 1 x x x 0 1 1 1 50 ms sets the energizing time (100% duty cycle) before 1 x x x 1 0 0 0 80 ms switching to pwm phase 1 x x x 1 0 0 1 110 ms 1 x x x 1 0 1 0 140 ms 1 x x x 1 0 1 1 170 ms 1 x x x 1 1 0 0 200 ms 1 x x x 1 1 0 1 230 ms 1 x x x 1 1 1 0 260 ms 1 x x x 1 1 1 1 300 ms 1 0 0 0 x x x x 0% output is off after energizing phase 1 0 0 1 x x x x 12.50% 12.5 khz 1 0 1 0 x x x x 25.00% 25 khz 1 0 1 1 x x x x 37.50% sets pwm chopping duty cycle. dc is the 1 1 0 0 x x x x 50.00% duty cycle that the low-side fet is on. 1 1 0 1 x x x x 62.50% 50 khz 1 1 1 0 x x x x 75.00% 1 1 1 1 x x x x 87.50% 22 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: drv8860 drv8860a
drv8860 , drv8860a www.ti.com slrs065d ? september 2013 ? revised october 2015 there are five operation cases as described in figure 27 through figure 31 . the output is turned on with 100% duty cycle. figure 27. case 1: timer enable bit (c8) is 0 (default value) the output is turned on in pwm chopping mode with duty cycle defined by control register bits c7:c5. figure 28. case 2: timer enable bit (c8) is 1 and energizing timing bits (c4:c1) are 0000 copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 23 product folder links: drv8860 drv8860a outx voltage (v) time (ms) vm outx current (ma) time (ms) dc*vm/r l pwm chopping outx voltage (v) time (ms) vm outx current (ma) time (ms) vm/r l max-on time
drv8860 , drv8860a slrs065d ? september 2013 ? revised october 2015 www.ti.com the output is turned on in energizing mode with 100% duty cycle for a duration set by control register bits c4:c1. after the timer expires, the output switches to pwm chopping mode with pwm duty cycle defined by control register bits c7:c5. figure 29. case 3: timer enable bit (c8) is 1, energizing timing bits (c4:c1) are not 0000, and pwm duty bits (c7:c5) are not 000 the output is turned on in energizing mode with 100% duty cycle for a duration set by control register bits c4:c1. after the timer expires, the output is turned off. figure 30. case 4: timer enable bit (c8) is 1, energizing timing bits (c4:c1) are not 0000, and pwm duty bits (c7:c5) are 00 24 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: drv8860 drv8860a outx voltage (v) time (ms) vm outx current (ma) time (ms) vm/r l max-on time outx voltage (v) time (ms) vm outx current (ma) time (ms) vm/r l dc*vm/r l max-on time pwm chopping
drv8860 , drv8860a www.ti.com slrs065d ? september 2013 ? revised october 2015 8.5.1.4.1 pwm start special command used the output is turned on in energizing mode with 100% duty cycle, and a timer is enabled with duration set by control register bits c4:c1. if the pwm start special command is received before the timer expires, then the output switches to pwm chopping mode with pwm duty cycle defined by control register bits c7:c5. if the timer expires and no pwm start is received, then the device will stay in energizing mode regardless of other pwm start commands. figure 31. case 5: timer enable bit (c8) is 0, energizing timing bits (c4:c1) are not 0000, and pwm duty bits (c7:c5) are not 000 copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 25 product folder links: drv8860 drv8860a outx voltage (v) time (ms) vm outx current (ma) time (ms) vm/r l dc*vm/r l max-on time pwm chopping p w m s t a r t
drv8860 , drv8860a slrs065d ? september 2013 ? revised october 2015 www.ti.com 8.6 register maps 8.6.1 data register the data register is used to control the status of each of the eight outputs: figure 32. data register d8 d7 d6 d5 d4 d3 d2 d1 out8 out7 out6 out5 out4 out3 out2 out1 r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset when any bit is ? 1 ? , the corresponding output will be active. when any bit is ? 0 ? , the output will be inactive. the data register is the default write location for the serial interface. in order to read back data from this register, the data register readout special command is used. 8.6.2 fault register the fault register can be read to determine if any channel exist fault condition. ocp is an overcurrent fault and old is an open load fault. old is not included on the drv8860a figure 33. fault register f16 f15 f14 f13 f12 f11 f10 f9 out8 ocp out7 ocp out6 ocp out5 ocp out4 ocp out3 ocp out2 ocp out1 ocp r/w r/w r/w r/w r/w r/w r/w r/w f8 f7 f6 f5 f4 f3 f2 f1 out8 ol out7 ol out6 ol out5 ol out4 ol out3 ol out2 ol out1 ol r/w r/w r/w r/w r/w r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset when any fault occurs, nfault pin will be driven low and corresponding fault register bit will be set up as ? 1 ? . ocp is a flag indicating overcurrent fault. odp is a flag indicating open load fault. fault bits can be reset by two approaches: 1. special command ? fault reset ? clear all fault bits. 2. setting data register to on will clear corresponding old bits (drv8860 only) setting data register to off will clear corresponding ocp bits. 8.6.3 control register the control register is used to adjust the energizing time and pwm duty cycle of outputs: figure 34. control register c8 c7 c6 c5 c4 c3 c2 c1 over all enable pwm duty cycle control energizing time control r/w r/w r/w legend: r/w = read/write; r = read only; -n = value after reset special command ? write control register ? is used to program control register. special command ? read control register ? is used to read back control register content. 26 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: drv8860 drv8860a
drv8860 , drv8860a www.ti.com slrs065d ? september 2013 ? revised october 2015 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the drv8860 is an eight channel low side driver with protection features. the following design is a common application of the drv8860. 9.2 typical application 9.2.1 design requirements table 3. design parameters parameter value input voltage range 8 v ? 38 v current 330 ma per channel copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 27 product folder links: drv8860 drv8860a latch out1 out2 out3 out4 out5 out6 out7 out8 vm gnd din clk dout nfault enable drv8860pwp ppad 0.1uf 10uf vm vm v3p3 4.7k ?
drv8860 , drv8860a slrs065d ? september 2013 ? revised october 2015 www.ti.com 9.2.2 detailed design procedure 9.2.2.1 drive current the current path is from vm, through the load, into the low-side sinking driver. power dissipation i 2 r losses in one sink are calculated using equation 1 . p d = i 2 x r ds(on) (1) 9.2.3 application curves figure 35. pwm operation 28 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: drv8860 drv8860a
drv8860 , drv8860a www.ti.com slrs065d ? september 2013 ? revised october 2015 10 power supply recommendations the drv8860 is designed to operate from an input voltage supply (vm) range between 8 and 38 v. a 0.1- f ceramic capacitor rated for vm must be placed as close as possible to the vm pin. in addition to the local decoupling cap, additional bulk capacitance is required and must be sized accordingly to the application requirements. bulk capacitance sizing is an important factor in motor drive system design. it is dependent on a variety of factors including: ? type of power supply ? acceptable supply voltage ripple ? parasitic inductance in the power supply wiring ? type of load ? load startup current the inductance between the power supply and motor drive system will limit the rate current can change from the power supply. if the local bulk capacitance is too small, the system will respond to excessive current demands or dumps from the motor with a change in voltage. the user should size the bulk capacitance to meet acceptable voltage ripple levels. the datasheet generally provides a recommended value but system level testing is required to determine the appropriate sized bulk capacitor. figure 36. example setup of motor drive system with external power supply 10.1 power supply and logic sequencing there is no specific sequence for powering-up the drv8860. it is okay for digital input signals to be present before vm is applied. after vm is applied to the drv8860, it begins operation based on the status of the control pins. copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 29 product folder links: drv8860 drv8860a local bulk capacitor parasitic wire inductance + motor driver power supply motor drive system vm gnd + ic bypass capacitor
drv8860 , drv8860a slrs065d ? september 2013 ? revised october 2015 www.ti.com 11 layout 11.1 layout guidelines ? the vm pin should be bypassed to gnd using a low-esr ceramic bypass capacitor with a recommended value of 0.1- f rated for vm. ? this capacitor should be placed as close as possible to the vm pin on the device with a thick trace or ground plane connection to the device gnd pin. ? the vm pin must be bypassed to ground using and appropriate bulk capacitor. this component must be located close to the drv8860. 11.2 layout example where the pull-up voltage (v3p3) is an external supply in the range of the recommended operating conditions for the digital open-drain outputs. figure 37. drv8860 layout 30 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: drv8860 drv8860a vm out1 din clk latch gnd dout nfault enable out2 out3 out4 out5 out6 out7 out8 10 f 0.1 f v3p3
drv8860 , drv8860a www.ti.com slrs065d ? september 2013 ? revised october 2015 11.3 thermal consideration the drv8860 device has thermal shutdown (tsd) as described in the thermal shutdown (tsd) section. if the die temperature exceeds approximately 150 c, the device is disabled until the temperature drops to a safe level. any tendency of the device to enter tsd is an indication of either excessive power dissipation, insufficient heatsinking, or too high of an ambient temperature. 11.3.1 power dissipation power dissipation in the drv8860 device is dominated by the power dissipated in the output fet resistance, r ds(on) . use the following equation to calculate the estimated average power dissipation of each output when running a driving a load. p d = r ds(on) x i o 2 where: ? p d is the power dissipation of one channel ? r ds(on) is the resistance of each fet ? i o is the rms output current being applied to each channel (2) i o is equal to the average current into the channel. note that at startup, this current is much higher than normal running current; these peak currents and their duration must be also be considered. the total device dissipation is the power dissipated in each channel added together. the maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heatsinking. note r ds(on) increases with temperature, so as the device heats, the power dissipation increases. this fact must be taken into consideration when sizing the heatsink. 11.3.2 heatsinking the powerpad package uses an exposed pad to remove heat from the device. for proper operation, this pad must be thermally connected to copper on the pcb to dissipate heat. on a multi-layer pcb with a ground plane, this connection can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. on pcbs without internal planes, a copper area can be added on either side of the pcb to dissipate heat. if the copper area is on the opposite side of the pcb from the device, thermal vias are used to transfer the heat between top and bottom layers. for details about how to design the pcb, refer to the ti application report, powerpad ? thermally enhanced package ( slma002 ), and the ti application brief, powerpad made easy ? ( slma004 ), available at www.ti.com . in general, the more copper area that can be provided, the more power can be dissipated. copyright ? 2013 ? 2015, texas instruments incorporated submit documentation feedback 31 product folder links: drv8860 drv8860a
drv8860 , drv8860a slrs065d ? september 2013 ? revised october 2015 www.ti.com 12 device and documentation support 12.1 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.2 trademarks powerpad, e2e are trademarks of texas instruments. all other trademarks are the property of their respective owners. 12.3 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.4 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 32 submit documentation feedback copyright ? 2013 ? 2015, texas instruments incorporated product folder links: drv8860 drv8860a
package option addendum www.ti.com 10-oct-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples drv8860apw active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 8860a drv8860apwr active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 8860a drv8860pw active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 8860 drv8860pwpr active htssop pwp 16 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 8860pwp drv8860pwr active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 8860 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device.
package option addendum www.ti.com 10-oct-2015 addendum-page 2 (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant drv8860apwr tssop pw 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 drv8860pwpr htssop pwp 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 drv8860pwr tssop pw 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 package materials information www.ti.com 9-oct-2015 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) drv8860apwr tssop pw 16 2000 367.0 367.0 35.0 drv8860pwpr htssop pwp 16 2000 367.0 367.0 35.0 drv8860pwr tssop pw 16 2000 367.0 367.0 35.0 package materials information www.ti.com 9-oct-2015 pack materials-page 2

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